Single crystal silicon grown by the Czochralski (Cz) technique is currently the most widely used semiconductor material for integrated circuits (ICs) in most applications. However, for higher frequency technologies, group III-V materials are generally preferred. This has meant that products such as mobile phones, which require both high and low frequency circuitry, are often constrained to using a hybrid arrangement, with group III-V semiconductors for the high frequency processes (e.g. front end signal processing in mobile phones) and silicon for the rest of the functionality of the device. Hybrid circuitry using group III-V semiconductors is complex and relatively expensive compared with solutions based on silicon wafers only. Group III-V materials also generally offer inferior thermal conductivity properties compared with silicon.
Recent improvements in silicon processing have led to an increase in the speed at which individual silicon devices can operate efficiently and the point has now been reached where individual Si-based devices are capable of operating at speeds approaching those of their III-V counterparts. However, using conventional production techniques, it is difficult to avoid the presence of background carriers in the silicon wafers, which leads to a reduced resistivity of the wafer. However high resistivity substrates are required for reducing transmission line losses, making high-Q inductors and minimising substrate crosstalk in high frequency applications and monolithic circuits. This degradation in the characteristics effectively prevents the use of silicon wafers for many high frequency devices.
To tackle these problems, several special processes have been described in the prior art for producing high resistivity substrates. These include the so-called float-zone (FZ) method for producing very high purity silicon and the “silicon-on-anything” (SOA) constructions in which a material other than a silicon wafer is used for the “handle” or base layer of the substrate (which is where most of the microwave power is absorbed).
Silicon wafers produced using the float-zone method can have resistivities of the order of 10 kΩcm or more, but their maximum diameter is typically limited to about 150 mm. This is unsuitable for modern VLSI technology where the standard wafer diameter is 300 mm. The other major problem of float zone wafers is the absence of oxygen, which internally getters metallic impurities in the substrate during device processing and improves reliability. Thus, float-zone substrates tend to have less reliable properties. There are also attempts to make high resistivity Cz silicon but these are presently limited to around 1 kΩcm and are more expensive than conventional Cz silicon wafers.
The use of thin films of GaN on silicon handle wafers is known for high power, high frequency architectures, but such approaches use relatively expensive float zone silicon.
The SOA technology uses an insulating material like quartz or glass for the handle layer instead of a silicon wafer, which has very different physical and thermal properties than silicon. This means processing apparatus and methods need to be adapted to the particular characteristics of the SOA devices. A further problem is the relatively high thermal resistances these devices present, which can be of the order of 15000 K/W rather than the usual 100 K/W. This can lead to substantial self-heating effects during operation and thermal runaway of devices even at low power levels.
Semicond. Sci. Technol. 18 (2003) 517-524 describes the use of deep level impurities to obtain “semi-insulating” (high resistivity) Czochralski (Cz) silicon. This academic study investigates values of deep impurity levels and their concentrations that are suitable for raising the resistivity of the silicon to near intrinsic levels. No details regarding commercial application of the technology are disclosed. Furthermore, the skilled person would be strongly disinclined to use the kind of impurities that act to increase the resistivity of silicon anywhere in a semiconductor manufacturing facility because of the risk of contamination of silicon device layers, which is known to seriously damage or destroy their performance.
WO 2009/034362 A1 discloses the use of deep level impurities to increase the resistivity of a substrate for high frequency circuits, but requires full encapsulation of the substrate, and/or of a device layer mounted on the substrate, by a diffusion barrier layer. Furthermore, substrates manufactured according to the teaching of WO 2009/034362 A1 can be sensitive to certain heat treatments that may be applied after the deep level impurities have been introduced into the substrate, for example to manufacture other elements of the electronic device of which the substrate is to be a part, or during operation of the electronic device. The subsequent heat treatments may cause the resistivity of the substrate to fall, in many cases to an unpredictable extent, which may reduce performance and/or affect reliability. It has also been found that a given process for impregnating a substrate with deep level impurities can result in a range of different resistivities, which hampers reliability and manufacturing efficiency (yield).